Integrated Circuits (ICs) rely on aluminum (Al) based interconnections to carry current to and from active devices (i.e., MOSFETS and Bipolar Transistors). Interconnections of copper (Cu) and gold (Au) have also been used and continue to be used for a limited number of applications. The reliability of these interconnections is generally limited by a phenomenon known as electromigration. Electromigration is the motion of atoms in a conductor due to the passage of current. It is basically a diffusional phenomenon with an applied electric field appearing to act as the driving force.
There are two mechanisms by which electromigration can lead to IC failure. In both cases, a net amount of Al migrates in the direction of the electron flow. In the first electromigration failure mechanism, a void is left behind at the negative end of the interconnection. As noted by R. H. Koch et al., 1/f Noise and Grain-Boundary Diffusion in Aluminum and Aluminum Alloys, Phys. Rev. Lett., Vol. 55(22), 2487-90 (1985), and by John G. J. Chern et al., Electromigration in Al/Si Contacts-Induced Open-Circuit Failure, IEEE Transactions on Electron Devices, Vol. ED-33(9), 1256-62 (1986), as the void grows due to continued Al mass transport, the resistance of the interconnection increases until an open circuit failure occurs. Single-layered metallizations typically show little or no resistance increase before failing catastrophically. In the case of multi-layered metallizations, a resistance increase is usually observed before catastrophic failure occurs. It has been shown that the resistance increase is caused by the depletion of Al. C-K. Hu et al., Electromigration in Al/W and Al(Cu)/W Interconnect Structures, Mat. Res. Soc'y Symp. Proc., Vol. 225, 99-105 (1991); C-K. Hu et al., Electromigration in Al(Cu) Two-Level Structures: Effect of Cu and Kinetics of Damage Formation, J. Appl. Phys. 74(2), 969-78 (1993).
In the second electromigration failure mechanism, an accumulation of Al occurs at the positive end of the interconnection. This accumulation causes pressure to be exerted on the surrounding insulator. As the pressure increases due to continued mass transport, cracks form in the insulator. The Al extrudes into the cracks in the insulator, causing a short circuit failure when the extruded material reaches an adjacent interconnection.
IC failure due to electromigration can only occur if there is a flux divergence. In thin-film conductors, flux divergences can be caused by both non-uniform structure and temperature gradients. Structural non-uniformities include grain boundaries, variation in grain size, and the presence of diffusion barriers. The interlevel tungsten (W) via used in Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) has introduced a barrier to Cu and Al diffusion between wiring levels. The presence of the W via has eliminated the so-called reservoir effect, thereby reducing the electromigration lifetime of multi-level test structures with W vias as compared to single level test structures C-K. Hu et al. Electromigration in Al/W and Al(Cu)/W Interonnect Structures, Mat. Res. Soc'y Symp. Proc., Vol. 225, 99-105 (1991); C-K. Hu et al., Electromigration in Al(Cu) Two-Level Structures: Effect of Cu and Kinetics of Damage Formation, J. App. Phys. 74(2), 969-78 (1993); R. G. Filippi et al., The Effect of Copper Concentration on the Electromigration Lifetime of Layered Aluminum-Copper (Ti--AlCu--Ti) Metallurgy With Tungsten Diffusion Barriers, VMIC Conf. Jun. 9-12, 1992, 359-65 (1992).
Traditionally, electromigration lifetimes have been described using a two-parameter log-normal distribution ##EQU1## where Z is th e inverse normal cumulative distribution function (CDF), t is the failure time, t.sub.50 is the median time to failure, and .sigma. is the shape parameter that measures the breadth in time during which failures occur. When plotted on log-normal probability paper, the failure times usually exhibit a good fit to a straight line. B. N. Agarwala et al., Dependence of Electromigration-Induced Failure Time on Length and Width of Aluminum Thin-Film Conductors, J. Appl. Phys., Vol. 41(10), 3954-60 (1970); J. R. Black, Electromigration of Al--Si Alloy Films, 16th Annual Proceedings of Reliability Physics, 233-40 (1978); H. P. Longworth et al., Experimental Study of Electromigration in Bicrystal Aluminum Lines, Appl. Phys. Lett. 60(18), 2219-21 (1992).
Recently, it was shown that the two-parameter log-normal distribution does not accurately describe early electromigration failures, resulting in paradoxical lifetime predictions. R. G. Filippi et al., Paradoxical Predictions and a Minimum Failure Time in Electromigration, Appl. Phys. Lett. 66(15), 1897-99 (1995)(hereafter "Paradoxical Predictions"). The apparent paradox was resolved by testing a large sample size and fitting the failure data to the three-parameter log-normal distribution ##EQU2## where t.sub.0 is the incubation time or the minimum time required before failure can occur.
FIG. 1 (taken from "Paradoxical Predictions") shows a log-normal CDF plot of the time to failure for 496 electromigration test samples. The samples were two-level structures having tungsten (W) stud-vias and titanium-aluminum copper-titanium (Ti--AlCu--Ti) metallization. The test conditions were 250.degree. C. and 1.88 MA/cm.sup.2, and the failure criterion was a +20% shift in resistance. The solid line represents the least-squares regression fit according to Equation (1) above while the dashed curve represents the least-squares regression fit according to Equation (2) above. Both the two- and three-parameter models reasonably fit the electromigration data between 5% and 95% cumulative failure. Clearly, the three-parameter model fits the data better than the two-parameter model at low (&lt;5%) cumulative failure.
FIG. 2 (taken from "Paradoxical Predictions") shows a log-normal CDF plot of the time to failure for 496 electromigration samples. Three different plots for three different failure criteria (10%, 20%, and 50% increase in resistance of test sample) are shown. Fitting the data for each failure criterion to Equation (2) results in t.sub.0 values of 4.70, 6.78, and 9.10 hours for failure criteria of +10%, +20%, and +50%, respectively. The minimum time required before failure can occur (t.sub.0) increases as the maximum allowed resistance change increases.
Evidence of a minimum time to failure has important implications for determining current densities at chip operating conditions. The results illustrated in FIGS. 1 and 2 suggest that the two-parameter log-normal distribution may overestimate the electromigration susceptibility of IC chips. If there is a minimum time required for electromigration failure, as the data indicate, then allowable operating current densities may be underestimated by using the two-parameter log-normal approach. This may impact the performance of certain IC chips and demonstrates the importance of testing a large sample size in electromigration experiments. For example, by using the three-parameter fit, circuit designers may be able to use higher currents while achieving the same reliability.
Conventional electromigration experiments are conducted at the chip level. Sample preparation is quite extensive for chip level experiments. Preparation involves dicing wafers into chips, mounting the chips onto substrates suitable for high temperature testing, and wire bonding from the test structure pads to the appropriate pins on the substrates. Usually, only one chip is mounted onto a single substrate, and only one or two test structures are wire bonded and stressed.
Wafer-level electromigration tests, such as the Standard Wafer-Level Electromigration Accelerated Test (SWEAT) as described by B. J. Root et al., Wafer Level Electromigration Tests For Production Monitoring, 23rd Annual Proceedings of Reliability Physics, 100-07 (1985), and the Breakdown Energy of Metal (BEM) Test as described by C. C. Hong et al., Breakdown Energy of Metal (BEM)--A New Technique for Monitoring Metallization Reliability at Wafer Level, 23rd Annual Proceedings of Reliability Physics, 108-14 (1985), avoid the sample preparation problems of conventional electromigration experiments. Wafer-level electromigration tests are conducted, however, at very high current densities (usually greater than 10 MA/cm.sup.2). Although sample preparation is extensive, chip-level testing is preferred for reliability measurements because it is difficult to correlate the results of tests at high current densities to actual operating conditions.
While the typical sample size for conventional electromigration experiments is less than 50, recent results suggest that larger sample sizes are necessary to accurately extrapolate stress results to operating conditions. R. G. Filippi et al., Paradoxical Predictions and a Minimum Failure Time in Electromigration, Appl. Phys. Lett. 66(15), 1897-99 (1995). Testing sample sizes much greater than 100 using conventional electromigration experiments is not practical considering the sample preparation time as well as the number of chips required for testing. Therefore, a need exists for testing a larger number of structures on a much smaller number of chips.
To overcome the shortcomings of conventional electromigration experiments, a new test layout is provided. An object of the present invention is to provide an improved test layout for detecting device failures by utilizing pad sharing. A related object is for the test layout to detect elecromigration failures caused by the first electromigration failure mechanism. Another object is for the test layout to detect elecromigration failures caused by the second electromigration failure mechanism. A further object is for the test layout to concurrently detect electromigration failures caused by both the first and second electromigration failure mechanisms.